Memory device equipped with data protection scheme

ABSTRACT

The present disclosure relates to a memory device comprising a hybrid memory portion in turn comprising a main nonvolatile memory and an auxiliary nonvolatile memory, and a controller configured to store data information in the main nonvolatile memory. The controller of the present disclosure comprises a parity engine configured to accumulate temporary parity information in the auxiliary nonvolatile memory, the parity information being associated with the data information stored in the main nonvolatile memory; when the parity information accumulated in the auxiliary nonvolatile memory is complete, the parity engine is further configured to transfer the complete parity information from the auxiliary nonvolatile memory to the main nonvolatile memory. A related apparatus and a related method are also disclosed.

PRIORITY INFORMATION

This application is a Continuation of U.S. application Ser. No.16/959,549, filed on Jul. 1, 2020, which is a U.S. National StageApplication under 35 U.S.C. § 371 of International Application NumberPCT/IB2019/000958, filed on Oct. 9, 2019, the contents of which areincorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to memory devices and more particularlyto a memory device equipped with data protection scheme.

BACKGROUND

Memory devices are used in many electronic systems such as mobilephones, personal digital assistants, laptop computers, digital camerasand the like. Nonvolatile memories retain their contents when power isswitched off, making them good choices for storing information that isto be retrieved after a system power-cycle.

Memory devices including nonvolatile flash memories, such as NANDmemories, need a data protection scheme to protect data from systemfailure, providing for a possibility of rebuilding lost or corrupteddata.

A known method for protecting data in memory devices is the use of ErrorCorrection Code (ECC), which is however often not enough to recover fulldata information.

Another method to contain the loss-data problem is Redundant Array ofIndependent NAND (RAIN). RAIN methods store the parity Exclusive Or(XOR) sum of independent NAND, so that in an event of failure, the lostdata may be recovered.

However, particularly in mobile applications, the controller of thememory devices usually accumulates partial parities into a dedicatedbuffer, so that there is the need to find a trade-off between SRAM sizeand write performance impact.

When parity is accumulated in the dedicated buffer, there is the need tosave and restore partial parity at power-cycles. Moreover, after powerloss, partial parities have to be rebuilt, which leads to reliabilityweakness, and no data protection is possible if a page read failureoccurs during this operation.

It is therefore desirable to avoid these drawbacks, as well as toimprove the operation of the controller of the memory devices,especially when RAIN protection is needed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a high-level block diagram of the memory device according tothe present disclosure;

FIG. 2 is a more detailed high-level block diagram of the memory deviceaccording to an embodiment the present disclosure;

FIG. 3 illustrates a traditional parity calculation;

FIG. 4 illustrates a parity calculation according to the presentdisclosure;

FIG. 5 illustrates logic for calculating parity in a memory device usingan auxiliary nonvolatile memory to accumulate parity according to thepresent disclosure;

FIG. 6 schematically shows a write path implemented by the memory deviceaccording to the present disclosure;

FIG. 7 schematically shows a write path implemented by the memory deviceaccording to an embodiment of the present disclosure;

FIG. 8 is a table illustrating a command implemented by the memorydevice according to the present disclosure; and

FIG. 9 is a flow diagram illustrating steps of a method according to thepresent disclosure.

DETAILED DESCRIPTION

With reference to those drawings, systems and methods involving a memorydevice equipped with data protection scheme will be disclosed herein.

More particularly, as it will be described into details in thefollowing, an example memory device comprises a hybrid memory portionincluding a main nonvolatile memory and an auxiliary nonvolatile memory,and a controller configured to store data information in the mainnonvolatile memory, wherein the controller is configured to accumulatetemporary parity information in the auxiliary nonvolatile memory, theparity information being associated with the data information stored inthe main nonvolatile memory, and wherein, when the parity informationaccumulated into the auxiliary nonvolatile memory is complete, thecontroller is further configured to transfer the complete parityinformation from the auxiliary nonvolatile memory to the mainnonvolatile memory.

Moreover, an example apparatus of the present disclosure comprises ahost device and a memory device apt to communicate with the host device,the memory device comprising a hybrid memory portion including a mainnonvolatile memory and an auxiliary nonvolatile memory, and a controllerconfigured to store data information into the main nonvolatile memory,the controller including a front-end for interfacing with the host and aback-end for interfacing with the hybrid memory portion, wherein theback-end is structured into a first portion adapted to interface withthe main nonvolatile memory and a second portion adapted to interfacewith the auxiliary nonvolatile memory, wherein the controller comprisesa parity engine arranged to connect the first portion of the back-endwith the second portion of the back-end and configured to accumulatetemporary parity information in the auxiliary nonvolatile memory, saidparity information being associated with the data information stored inthe main nonvolatile memory, and wherein, when the parity informationaccumulated into the auxiliary nonvolatile memory is complete, theparity engine is configured to transfer the complete parity informationfrom the auxiliary nonvolatile memory to the main nonvolatile memory

The present disclosure also relates to a method for operating a memorydevice, comprising the steps of storing data information in a mainnonvolatile memory, accumulating temporary parity information in anauxiliary nonvolatile memory, said parity information being associatedwith the data information stored in the main nonvolatile memory, andwhen the parity information is complete, transferring the completeparity information from the auxiliary nonvolatile memory to the mainnonvolatile memory.

Nonvolatile memories retain their contents when power is switched off,making them good choices for storing information that is to be retrievedafter a system power-cycle.

A Flash memory is a type of nonvolatile memory that retains stored dataand is characterized by a very fast access time. Moreover, it can beerased in blocks instead of one byte at a time. Each erasable block ofmemory comprises a plurality of nonvolatile memory cells arranged in amatrix of rows and columns. Each cell is coupled to an access lineand/or a data line. The cells are programmed and erased by manipulatingthe voltages on the access and data lines.

FIG. 1 is a schematic block diagram of a memory device 100 according tothe present disclosure.

The memory device 100 comprises a memory controller 110 and a hybridmemory portion 120 including a main nonvolatile memory 121 (hereinreferred to also as nonvolatile memory chip) for data storage.

According to an embodiment of the present disclosure, the mainnonvolatile memory 121 comprises a plurality of NAND dies 121′.

Each NAND die 121′ may comprise one or more Plane data structures. EachPlane data structure may comprise one or more Block data structures.Each Block may comprise multiple Physical Rows. Each Physical Row maycomprise multiple Page data structures. In the NAND memory system, allthe Planes may be active simultaneously. A single read access in a NANDsystem may involve one Page per Plane, where pages may be readsimultaneously. An erase operation in a NAND memory system may involveone Block per Plane, where Blocks are also erased simultaneously.

The controller 110 can include an embedded firmware and is adapted tomanage and control the operation of the hybrid memory portion 120. Thecontroller 110 may be coupled to hybrid memory portion 120 through buses130′, 130″. More in particular, the controller 110 is configured tostore data information in the main nonvolatile memory 121.

An operating system OS and one or more applications may be executed onthe controller 110. The OS of the controller 110 may request memory inthe hybrid memory portion 120 on behalf of the one or more applications.In some embodiments, the controller 110 may be a system-on-chip (SOC)performing memory operations on the hybrid memory portion 120.

Clearly, the memory device 100 can also comprise other components, suchas processor units coupled to the controller 110, antennas, connectionmeans (not shown), and the like.

The controller 110 is responsible for interfacing the hybrid memoryportion 120 with a host device 140 and for the programming of the memorydevice 100. In particular, the controller 110 is configured tocommunicate with the host device 140 and to exchange data informationtherewith.

According to an embodiment, the host device 140 is a mobile phone andthe memory device 100 is a Universal Flash Storage (UFS) for datastorage of said mobile phone.

Memory devices including flash memories, such as NAND memories, need adata protection scheme to protect data information from system failure.

A well-known method to contain the loss-data problem and manage on-fielddefectivity is Redundant Array of Independent NAND (RAIN). RAIN methodsstore the parity Exclusive Or (XOR) sum of data stored, so that in anevent of failure, the lost data may be recovered, as it will be detailedin the following.

Usually, there are three kinds of failures that can be tackled by usingRAIN, namely word line (WL) corruption due to program failures (PFs),normal Uncorrectable ECC (UECC), and lower page (LP) corruption due toasynchronous-power-loss (APL).

Advantageously according to the disclosure, the hybrid the memoryportion 120 comprises, in addition to the main nonvolatile memory 121 anauxiliary nonvolatile memory 122, and the controller 110 is configuredto accumulate in this auxiliary nonvolatile memory 122 temporary parityinformation associated with the data information stored in the mainnonvolatile memory 121.

More particularly, referring now to memory device 200 of FIG. 2(corresponding to the memory device 100 of FIG. 1 ), the controller 210comprises a parity engine 250 configured to store the temporary parityinformation in the auxiliary nonvolatile memory 222 of the hybrid memoryportion 220. The auxiliary nonvolatile memory 222 is therefore able toaccumulate parity values when directed by a command from the controller210, in particular from the parity engine 250. In the following, theparity engine 250 will be referred to also as parity module or RAINengine.

In other words, according to the present disclosure, memory paritycalculation and storage schemes protect data information by using thecontroller 210 (in particular the parity engine 250) to calculate parityvalues, and then writing the generated parity values to the auxiliarynonvolatile memory 222 of the memory portion 220.

Advantageously, the controller 210 of the present disclosure isstructured and programmed in such a way that system overhead during readand write operations to calculate and store parity are avoided, and agreat efficiency is achieved.

According to an embodiment of the present disclosure, the auxiliarynonvolatile memory 222 of the memory portion 220 is a 3D X Point (3DXP)memory. The auxiliary nonvolatile memory 222 can also be a Phase ChangeMemory (PCM) or also a Chalcogenide-based memory or Self-SelectingMemory. However, the auxiliary nonvolatile memory function may also beprovided by any other known or emerging technology memory type, such asFerroelectric RAM (FeRAM), Spin Transfer Torque Magnetic RAM (STTMRAM).

In general, the requirements of the auxiliary nonvolatile memory 222 arelow latency, bit alterability (for example for implementing embeddedcommands) and high density of the memory (e.g. at the giga level). Inthis respect, the 3DXP memory is the best candidate to act as auxiliarynonvolatile memory 222.

According to an embodiment of the disclosure, the controller 210comprises a front-end FE configured to interface with the host device240, a middle-end ME, and a back-end BE configured to interface with thehybrid memory portion 220, wherein the back-end BE is structured into afirst portion BE1 adapted to interface with the main nonvolatile memory221 and a second portion BE2 adapted to interface with the auxiliarynonvolatile memory 222, such portions communicating via suitable buses.

Furthermore, the memory device 200 may comprise other components, suchas analog blocks 260 and other peripherals without limiting the scope ofthe disclosure. A volatile SRAM is included as in any traditionalmicrocontroller.

According to an embodiment, the main nonvolatile memory may beconfigured to implement a low-density parity-check (LDPC) code as errorcorrection code, while the auxiliary nonvolatile memory may beconfigured to implement a BCH code for encoding/decoding.

Referring again to the example of FIG. 2 , all the data, before beingwritten in the main nonvolatile memory, pass through a scrambler.

The possibility to accumulate temporary parity information in theauxiliary nonvolatile memory 222 is therefore advantageous because suchmemory is very reliable does not need RAIN protection and no trade-oftrade-offs between SRAM size and write performance impact has to befound. The auxiliary nonvolatile memory 222 is therefore used as a RAMof the traditional solution but it is nonvolatile (and thus temporaryparity information therein is maintained also in case of power loss) andhas very low latency time. The efficient use of the auxiliarynonvolatile memory as a buffer is possible thanks to an improvedarchitecture of the controller, as it will be disclosed below.

In order to highlight the advantages of the system and method of thepresent disclosure, a comparison with the traditional system and methodis now performed. FIG. 3 illustrates the parity calculation for atraditional memory device, comprising a NAND flash memory. In suchmemory system, scaling nodes of NAND Flash technology under 20 nmdeteriorates the reliability of the memory in such a way that theprobability of on-field Word-Line (WL) shorts are not negligible. Aspreviously mentioned, a well-known method to contain the loss-dataproblem caused by WL-WL shorts is RAIN, which stores the parityExclusive Or (XOR) sum of independent NAND pages of a memory stripearea, so that in an event of failure, the lost data in the WL-WL shortmay be recovered.

As shown, the parity calculation is typically performed by accumulatingintermediate parity values into a dedicated buffer, therefore having animpact on the performances of the RAM or SRAM. The XOR program isexecuted by summing all of the memory page structures to be protected.In other words, the parity P is calculated as:

P+Σ _(i=1) ^(n) D _(i) =D _(j)+Σ_(i=1(u≠j)) ^(n) D _(i)  (1)

where D₁, D₂, . . . , D_(n) are the data of the n pages (e.g., D_(i) isthe data of page i).

Saving the parity of n pages allows for recovering an original page ofdata from a page that may have been lost or corrupted. For example, dataD_(j) for page j may be recovered by subtracting the parity sum of allpages except page j from the total parity sum, P, as shown below:

D _(j) =P−Σ _(i=1(i≠j)) ^(n) D _(i)  (2)

Especially in mobile applications, a multi-page RAIN is adopted, whereinthe parity is calculated by the controller and then accumulated in adedicated buffer before being written in the NAND, as shown in FIG. 3 .As previously mentioned, a trade-offs between SRAM size and writeperformance impact has to be found, so that, for instance, 348 kB ofSRAM size has an impact of 7%, 640 kB of SRAM size has an impact of3.5%, and 4.6 MB of SRAM size has potentially no impact. Moreover,partial parity has to be saved and restored at power cycles, and afterpower loss, partial parities have to be rebuilt in SRAM, leading toreliability weakness: if there is a page read failure during thisoperation there is no RAIN protection. This traditional method has avery strong impact on the RAM performances.

According to the present disclosure, the above-mentioned drawbacks areovercome. As shown in FIG. 4 , in the memory device 400 (correspondingto the memory devices 100 and 200 of FIGS. 1 and 2 ) the parity iscalculated via the controller (specifically via the parity engine 450)according to the above formulas, and then temporary parity isaccumulated in the auxiliary nonvolatile memory 422 while datainformation is stored in the main nonvolatile memory 421. Parityinformation is transferred from auxiliary memory 422 to main nonvolatilememory 421 when it is complete, obtaining many advantages, as it will bedescribed in more details below.

FIG. 5 illustrates logic for calculating parity in a memory device 500using an auxiliary nonvolatile memory 522 to accumulate parity. In alogical representation of a RAIN parity value calculation and storageoperation 500 a, pages D1-D8 are summed by summers S1-S7 to produce aparity P for pages D1-D8 according to Equation 1 above. Pages D1-D8 arewritten to the main nonvolatile memory 521 and the new parity P iswritten to the auxiliary nonvolatile memory 522. Then, in a logicalrepresentation of a RAIN parity data restoration operation 500 b,missing or corrupted data recovery of page D2 may comprise readingundamaged data pages D1 and D3-D8 from the main nonvolatile memory 521and the parity value P from the auxiliary nonvolatile memory 522. Pagerecovery is performed by the controller 510 by comparing the partiallyrecalculated parity value with the stored parity value according toEquation 2 in order to restore the original data page D2.

All the operations are performed in the controller of the memory device.As previously mentioned, advantageously, the controller according to thepresent disclosure comprises the parity engine which accumulatestemporary partial parity information in the auxiliary nonvolatilememory, the parity information being associated with the datainformation stored in the main nonvolatile memory. Then, only when theparity information is complete, the parity engine is further configuredto transfer the complete parity information from the auxiliarynonvolatile memory to the main nonvolatile memory, so that the parity isrecalled only when it is complete and has to be sent to the mainnonvolatile memory, i.e. to the NAND.

In other words, in response to the completion of the accumulated parity,the parity engine is arranged to connect the main nonvolatile memory andthe auxiliary nonvolatile memory for the transfer of the totalaccumulated parity, greatly simplifying the operation of the controller.

Referring now to data path of the memory device 600 FIG. 6(corresponding to the memory devices 100, 200, 400 and/or 500), thecontroller 610 comprises a front-end FE configured to interface with thehost device 640 and a back-end BE configured to interface with thehybrid memory portion 620, wherein the back-end is structured into afirst portion BE1 adapted to interface with the main nonvolatile memory621 and a second portion BE2 adapted to interface with the auxiliarynonvolatile memory 622.

More in particular, advantageously according to the new controllerconfiguration, the parity engine 650 lies at the intersection of thefirst portion BE1 of the back-end (i.e. the NAND back-end) and thesecond portion BE2 of the back-end (i.e. the auxiliary nonvolatilememory back-end). In this way, the parity engine 650 is arranged toconnect the first portion BE1 of the back-end with the second portionBE2 of theback end for the transfer of the complete parity informationfrom the auxiliary nonvolatile memory 622 to the main nonvolatile memory621. This improves the performances of the controller, as data are notaccumulated in the RAM anymore, and the same time simplifying theoperation of said controller.

In an embodiment, due to the improved architecture of the controller,the controller 610 is configured to store the data information in themain nonvolatile memory 621 simultaneously with the accumulation of thetemporary parity information in the auxiliary nonvolatile memory 621.Moreover, the architecture of the controller allows for a simultaneouswrite operation in the main nonvolatile memory and read operation in theauxiliary nonvolatile memory.

As previously stated, the auxiliary nonvolatile memory is thusefficiently used to accumulate the temporary parity information, so thatbasically no space of the SRAM is used (only 32 kB are used to performthe accumulation of the temporary parity) and no RAIN buffer is used(since the auxiliary nonvolatile memory is used as a buffer). In anembodiment, the controller may also be configured to save the completeparity information into the auxiliary nonvolatile memory, so as to savespace in the main nonvolatile memory, even if, especially in mobileapplication, it is preferred to transfer and save the complete parity tothe main NAND memory.

In an embodiment, as shown in FIG. 7 , based on the dimension and/ortype of the data information to be written in the hybrid memory portion,the controller is configured to select whether to write the datainformation directly into the auxiliary nonvolatile memory, withoutaccumulating parity information or to write the data information intothe main nonvolatile memory, while accumulating parity information andtransfer the parity from the auxiliary nonvolatile memory to the mainnonvolatile memory once said parity is complete. The first option, i.e.a direct write in the auxiliary memory, could be useful for small chunk,while for large chunk it is preferable to write data information in themain nonvolatile memory.

More in particular, in the memory device 700 (corresponding to device100, 200, 400, 500 and/or 600) of FIG. 7 , the controller 710 comprisesa volatile cache 711 where data information are accumulated before beingwritten into the hybrid memory portion 720, and then, based on the data,the controller 710 selects the proper data path.

Summing up, according to the present disclosure, the controller of thememory device is configured to accumulate the temporary parity in thenonvolatile auxiliary memory, the parity being sent to the main NANDmemory chip once it is completed. In this way, traditional multipageRAIN, in which the parity is written in a dedicated RAIN buffer of theSRAM, is avoided and only ˜32 kB of the SRAM are now used foraccumulating parity, due to the support of the auxiliary nonvolatilememory. This has no impact on write performance and no save/loadoperation at power cycles need to be performed, as the parity isaccumulated in a nonvolatile memory, which can be chosen so as to beextremely reliable and not in the RAM. Moreover, there is no consequencedue power loss and data can always be efficiently recovered.

The operation of the controller is extremely improved because the RAINengine is arranged at the intersection of main NAND memory and theauxiliary nonvolatile memory back-end, so that the controller writes thetotal parity in the NAND only when the accumulated parity is complete.In this way, the data in the nonvolatile memory is recalled only when itis needed. In other words, the parity engine is configured to transferdata from the two nonvolatile memories when parity is complete and noteach time the parity is to be updated. The controller architecture istherefore suitably modified so that the auxiliary nonvolatile memory isefficiently used a SRAM buffer, without impact on the systemperformances.

The present disclosure also provides for a further optimization of thememory controller, achieving an even more reduced system overhead duringmemory write and read operations respectively.

In particular, this second step of optimization provides foraccumulating the parity calculation in the auxiliary nonvolatile memoryitself by superimposing new (i.e. updated) parity data over oldpreviously calculated parity information (or on empty memory locationsin case no previous parity information is available). This introduces anew internal self-accumulating parity program component in the auxiliarynonvolatile memory for reducing time and power consumption byeliminating unnecessary reading and writing between the controller andthe auxiliary nonvolatile memory. Execution of this internal programcomponent is realized by introducing a new command in the auxiliarynonvolatile memory. In one embodiment, the program command is an “XORprogram” command.

In particular, when the command “XOR program” is received (for examplefrom the controller) with address and input data parameters, stored datais read at the input address and an XOR operation of the read data andnew input data is performed and the results of the computation arewritten into memory, typically at same location of the input addressreceived with XOR program command. However, a second address may beinput with the command for storing the result of the XOR computation ata second address (e.g., read at the first address, and write at secondaddress).

When the XOR command is received in operation, a program internal to thehybrid memory portion for computing and storing an XOR result of readdata and input data is performed, e.g., by reading data stored at theinput address, computing the XOR of the read data and the input dataaccording to an XOR Program rule, and writing the result in memory.

In this case, the memory chip is suitably modified so that theself-Accumulating Exclusive OR Program accumulates the parity result inmemory cells internal to the auxiliary nonvolatile memory system itselfwithout intervention by the external controller. The program is thusdirectly executed by the memory chip after receiving a program command.

In other words, the hybrid memory portion is configured to execute aninternal program in response to a program command from the controller,wherein the auxiliary nonvolatile memory, based on said internalprogram, is configured to store the parity information by overwritingold parity information with new parity information according to anExclusive OR (XOR) program rule, wherein the auxiliary nonvolatilememory is apt to execute said internal command to overwrite or keep theold parity information without intervention from the controller, whereinthe previous parity information is associated with first datainformation stored in the main nonvolatile memory and the updated parityinformation is associated with second data information different fromthe first data information.

The updated parity information is included in an accumulated parity sumof data stored in the memory system for recovering an original data froma corrupted data in the memory system.

More in particular, the memory portion is configured to overwrite theold parity information stored in the auxiliary nonvolatile memory withthe new parity information regardless of a value of the old parityinformation if the new parity information has a first value, or to keepthe old parity information at a same value if the new parity informationhas a second value, the second value being different from the firstvalue.

This new modification to the memory chip allows achieving reduced systemoverhead during memory write and read operations in the memory systemand to reduce time and power consumption.

In one exemplary embodiment, a 16 KB NAND page has a 4 planes per pagearchitecture. Parity is a 16 KB vector calculated as

P=Σ _(i=1) D _(i)  (3)

where n=16 is the number of pages that are readable or programmable at atime. In other words, the stripe dimension is equal to a number of NANDdie in the nonvolatile memory multiplied by the number of planes in eachNAND device, while D_(i) is the 16 KB page of the i-th plane. Becausethe parity sum is an exclusive logic sum (XOR), it is possible toretrieve lost data D_(i), caused by a failure on the j-th page, by meansof subtraction:

D _(j)=Σ_(i=1(i≠j)) D _(i) −P  (4)

Thus, it is also possible to write;

D _(j)=Σ_(i=1(i≠j)) D _(i) +P   (5)

(i.e. the lost data is the XOR of the saved parity with the paritycalculated excluding the irretrievable page D_(i)).

The traditional program rule is modified inside the memory portion tocreate an XOR program rule for supporting a Self-Accumulating ExclusiveOR Program. The Traditional Program Rule is shown in Table of FIG. 8 ,which is replaced by the new program rule, shown in the same Table ofFIG. 8 .

The XOR Program Rule according to the present disclosure allows theexecution of the self-accumulating parity program to occur directly inthe auxiliary nonvolatile memory, producing time and power savings inboth partial write events and in the second XOR evaluation operation.The modified XOR Program Rule replaces the Traditional Program Ruleshown, using temporary storage areas for calculations. In this way, theself-Accumulating Exclusive OR Program establishes a new program commandin the auxiliary memory system, that uses the XOR Program Rule of FIG. 8rather than the Traditional Program Rule.

Read and write performance conditions are determined by thecharacteristics of two channels shared by multiple NAND devices and oneauxiliary memory memory system with serialized transmission of data, andindependent NAND and auxiliary memory planes that can be written andread in parallel.

As previously mentioned, Self-Accumulating Exclusive OR Program systemmethodology begins by receiving the specific command. Then parity isaccumulated in the auxiliary memory according to Equation 1 and the newXOR Program Rule of the table of FIG. 8 , by superimposing previouslystored parity information with new parity information.

More in particular, according to the traditional program rule, when apreviously stored parity bit has a value of 0 and a new parity bit valueis also equal to 0, no new parity bit value is superimposed in aninternal storage memory cell of the auxiliary memory system's parityvalue. When a previously stored parity bit has a value of 0 and a newparity bit value is equal to 1, a new parity bit value of 1 issuperimposed in the corresponding internal parity memory cell of theauxiliary memory system over the previous value of 0. In other words, aSet operation is performed, wherein a Set operation refers to theoperation of programming a bit to 1.

When a previously stored parity bit has a value of 1 and a new paritybit value is equal to parity bit value of 0, a 0 value is superimposedin the auxiliary memory system's internal parity storage memory cell. Inother words, a Reset operation is performed, wherein a reset operationrefers to the operation of programming a bit to 0. When a previouslystored parity bit has a value of 1 and a new parity bit value is alsoequal to 1, no new parity bit value is superimposed in an internalstorage memory cell of the auxiliary memory system's parity value (e.g.,it remains at 1). However, these operations cannot be performed directlyin the auxiliary memory.

Rather than the Traditional Program rule, Self-Accumulating Parity forMemory uses the new XOR program rule. The effect of the new XOR ProgramRule is to realize an XOR operation directly in the memory device,saving time as well as power during partial writes and during the secondoperation of the RAIN XOR evaluation that sums parities for even and oddpages, while read accesses by the controller are eliminated entirely.

Each memory cell is pulsed according to the new XOR Program Rule. Incontrast to the Traditional Program Rule, the new XOR Program Rulecauses a reset pulse when the stored bit is equal to 1 and the new bitis also equal to 1. The XOR Program Rule causes a set pulse when thestored bit is equal to 0 and the new bit is equal to 1. In the remainingtwo cases where the new bit is equal to 0, the internal memory cell isnot pulsed (so it remains at 0 or at 1). Therefore, when a previouslystored parity bit has a value of 0 and a new parity bit value is equalto 1, a new parity bit value of 1 is superimposed in the correspondinginternal parity memory cell of the auxiliary memory over the previousvalue of 0. In other words, a Set operation is performed, wherein a setoperation refers to the operation of programming a bit to 1. When apreviously stored parity bit has a value of 1 and a new parity bit valueis equal to 0, no new parity bit value is superimposed in an internalstorage memory cell of the auxiliary memory system's parity value (e.g.,it remains at 1). When a previously stored parity bit has a value of 1and a new parity bit value is also equal to 1, parity bit value of 0 issuperimposed in the auxiliary memory system's internal parity storagememory cell. In other words, a Reset operation is performed, wherein areset operation refers to the operation of programming a bit to 0. Whena previously stored parity bit has a value of 0 and a new parity bitvalue is also equal to 0, no new parity bit value is superimposed in aninternal storage memory cell of the auxiliary memory system's parityvalue (e.g., it remains at 0).

Thus, an auxiliary memory element is programmed to accumulate and storea parity sum by setting and resetting previously stored parity bitvalues according to conditions defined by an Exclusive Or (XOR) truthtable, shown in FIG. 8 , without intervention of the controller. Eachnewly calculated bit value is superimposed in the corresponding finalinternal bit storage location, (e.g., the parity memory cell) of theauxiliary memory system.

This internal read for XORing the current content of a page with a newdata pattern has the great advantage that the reading of partialparities from the auxiliary nonvolatile memory is avoided.

More in particular, a reduced system overhead during write operations isobtained. In fact, during partial (or intermediate) write operations,the controller generates time and power overhead by reading the previousparity stored in the auxiliary memory. On the contrary, using the newSelf-Accumulating Exclusive OR Program methodology, the existing paritydata stored in the auxiliary memory may be up-dated at each partialwrite operation directly with the parity of page, or pages, written (forexample directly with input data written in a single page Dk of NANDflash). Self-Accumulating Exclusive OR Program methodology eliminatesreading of the previous parity stored in the auxiliary memory by thecontroller, eliminating the time and energy overhead during partialwrite operations.

Finally, according to the present disclosure, a method 900 for operatinga memory device, comprises the step 910 of storing data information in amain nonvolatile memory, a step 920 of accumulating temporary parityinformation in an auxiliary nonvolatile memory, said parity informationbeing associated with the data information stored in the mainnonvolatile memory, and a final step 930 of transferring, when theparity information is complete, the complete parity information from theauxiliary nonvolatile memory to the main nonvolatile memory.

In the preceding detailed description, reference is made to theaccompanying drawings that form a part hereof, and in which is shown, byway of illustration, specific examples. In the drawings, like numeralsdescribe substantially similar components throughout the several views.Other examples may be utilized, and structural, logical and/orelectrical changes may be made without departing from the scope of thepresent disclosure. In addition, as will be appreciated, the proportionand the relative scale of the elements provided in the figures areintended to illustrate the embodiments of the present disclosure andshould not be taken in a limiting sense.

As used herein, “a,” “an,” or “a number of” something can refer to oneor more of such things. A “plurality” of something intends two or more.As used herein, the term “coupled” may include electrically coupled,directly coupled, and/or directly connected with no intervening elements(e.g., by direct physical contact) or indirectly coupled and/orconnected with intervening elements. The term coupled may furtherinclude two or more elements that co-operate or interact with each other(e.g., as in a cause and effect relationship).

Although specific examples have been illustrated and described herein,those of ordinary skill in the art will appreciate that an arrangementcalculated to achieve the same results can be substituted for thespecific embodiments shown. This disclosure is intended to coveradaptations or variations of one or more embodiments of the presentdisclosure. It is to be understood that the above description has beenmade in an illustrative fashion, and not a restrictive one. The scope ofone or more examples of the present disclosure should be determined withreference to the appended claims, along with the full range ofequivalents to which such claims are entitled.

1. A memory device, comprising: a hybrid memory portion including a main nonvolatile memory and an auxiliary nonvolatile memory; and a controller, comprising: a front-end configured to interface with a host device; and a back-end configured to interface with the hybrid memory portion, wherein the back-end is structured into a first portion adapted to interface with the main nonvolatile memory and a second portion adapted to interface with the auxiliary nonvolatile memory; and wherein the controller is configured to: store data information in the main nonvolatile memory; accumulate parity information in the auxiliary nonvolatile memory, the parity information associated with the data information stored in the main nonvolatile memory; and responsive to completion of accumulating the parity information into the auxiliary nonvolatile memory, transfer the complete parity information from the auxiliary nonvolatile memory to the main nonvolatile memory.
 2. The memory device of claim 1, wherein the accumulated parity information is a Redundant Array of Independent NAND (RAIN) parity calculated by an Exclusive OR (XOR) program.
 3. The memory device of claim 1, wherein the controller is configured to store the data information in the main nonvolatile memory simultaneously with the accumulation of the parity information in the auxiliary nonvolatile memory.
 4. The memory device of claim 1, wherein the controller is configured to save the complete parity information into the auxiliary nonvolatile memory.
 5. The memory device of claim 1, wherein the main nonvolatile memory comprises a plurality of NAND dies.
 6. The memory device of claim 1, wherein the auxiliary nonvolatile memory is a 3D X Point (3DXP) memory.
 7. The memory device of claim 1, wherein the auxiliary nonvolatile memory is a phase change memory (PCM) or a chalcogenide memory.
 8. The memory device of claim 1, wherein the main nonvolatile memory is configured to implement a low-density parity-check (LDPC) code.
 9. The memory device of claim 1, wherein the auxiliary nonvolatile memory is configured to implement a Bose-Chaudhuri-Hocquenghem (BCH) code.
 10. The memory device of claim 1, comprising the controller configured to select whether to write the data information directly into the auxiliary nonvolatile memory without accumulating parity information or to write the data information into the main nonvolatile memory while accumulating parity information based on a dimension of the data information to be written in the hybrid memory portion, a type of the data information to be written in the hybrid memory portion, or a combination thereof.
 11. The memory device of claim 1, comprising: the hybrid memory portion configured to execute an internal program in response to a program command from the controller; the auxiliary nonvolatile memory configured to: store, based on the internal program, the parity information by overwriting old parity information with new parity information according to an Exclusive OR (XOR) program rule; and execute the internal command to overwrite or keep the old parity information without intervention from the controller, wherein the previous parity information is associated with first data information stored in the main nonvolatile memory and the updated parity information is associated with second data information different from the first data information.
 12. A method for operating a memory device, comprising: storing data information in a main nonvolatile memory, the main non-volatile memory interfacing with a first portion of a back-end of a controller that interfaces with a hybrid memory portion of the memory device; accumulating parity information in an auxiliary nonvolatile memory, the auxiliary non-volatile memory interfacing with a second portion of the back-end of the controller, and the parity information associated with the data information stored in the main nonvolatile memory; responsive to completion of accumulating the parity information, transferring the complete parity information from the auxiliary nonvolatile memory to the main nonvolatile memory; and connecting the first portion of the back-end of the controller with the second portion of the back end of the controller to transfer the complete parity information from the auxiliary non-volatile memory to the main non-volatile memory.
 13. The method of claim 12, comprising simultaneously storing data information in the main nonvolatile memory and accumulating parity information in the auxiliary nonvolatile memory.
 14. The method of claim 12, comprising selecting, based on the dimension of data to be written, type of data information—to be written, or a combination thereof, whether to write the data information into the auxiliary nonvolatile memory without accumulating parity information or to write the data information into the main nonvolatile memory while accumulating parity information.
 15. The method of claim 12, comprising: executing, in a memory portion of the memory device, an internal program in response to a program command from a controller, wherein executing the internal program comprises: the auxiliary nonvolatile memory storing, based on the internal program, the parity information by overwriting old parity information with new parity information according to an Exclusive OR (XOR) program rule; and the auxiliary nonvolatile memory overwriting or keeping the old parity information without intervention from the controller responsive to the memory system receiving the program command, wherein: the previous parity information is associated with first data information stored in the main nonvolatile memory; and the new parity information is associated with second data information different from the first data information, the new parity information included in an accumulated parity sum of data stored in the memory portion for recovering an original data from a corrupted data.
 16. The method of claim 15, comprising: overwriting the old parity information stored in the auxiliary nonvolatile memory—with the new parity information regardless of a value of the old parity information responsive to the new parity information having a first value; and keeping the old parity information at a same value responsive to the new parity information having a second value different from the first value.
 17. The method of claim 12, comprising: passing the data information saved into the main nonvolatile memory through a data scrambler; and passing the data information and the accumulated complete parity information through a low-density parity-check (LDPC) encoder in the main nonvolatile memory.
 18. A memory apparatus comprising: a host device; and a memory device coupled to the host device, the memory device comprising: a hybrid memory portion including a main nonvolatile memory and an auxiliary nonvolatile memory; and a controller configured to store data information into the main nonvolatile memory, and comprising: a front-end for interfacing with the host device; a back-end for interfacing with the hybrid memory portion and structured into a first portion configured to interface with the main nonvolatile memory and a second portion configured to interface with the auxiliary nonvolatile memory; and a parity engine configured to: connect the first portion of the back-end with the second portion of the back-end; accumulate parity information in the auxiliary nonvolatile memory, the parity information associated with the data information stored in the main nonvolatile memory; and responsive to completion of accumulation of the parity information into the auxiliary nonvolatile memory, transfer the complete parity information from the auxiliary nonvolatile memory to the main nonvolatile memory via the connected first portion of the back-end and the second portion of the back-end. 